The present invention relates to a chopper comparator formed in a semiconductor integrated circuit, and more particularly to a chopper comparator showing high speed and low power operations free of malfunction under variation of a logical threshold voltage of an invertor.
The chopper comparator has been used as a voltage comparator for an analog-to-digital converter for converting analog signals to digital signals. The chopper comparator judges whether a voltage level of analog signals inputted is higher or lower than a comparative reference voltage. One of the chopper comparators is disclosed in IEEE Journal of Solid State Circuit, Vol. SC-20, No. 6, pp. 1138-1143, December 1985.
A conventional chopper comparator will be described with reference to FIGS. 1 and 2. FIG. 1 is a circuit diagram illustrative of the conventional chopper comparator. FIG. 2 is a timing chart illustrative of signal waveforms of the conventional chopper comparator. The conventional chopper comparator has two input terminals 8 and 9. An analog input voltage Vin is applied to the input terminal 8. A comparative reference voltage Vref is applied to the input terminal 9. The input terminal 8 is connected through a first switch 1 to a first capacitor C21. The input terminal 9 is connected through a second switch 2 to the first capacitor C21. The first capacitor C21 is applied either the analog input voltage Vin or the reference voltage Vref. The conventional chopper comparator has a first invertor 23 having an input terminal connected to the first capacitor C21. The conventional chopper comparator has a second capacitor C22 connected to an output terminal of the first invertor 23. A third switch 19 is provided between the input and output terminals of the first invertor 23 so that the third switch 19 and the first invertor 23 are connected in parallel to each other to the first capacitor C21. A second invertor 24 is provided having an input terminal connected to the second capacitor C22. A fourth switch 20 is provided between input and output terminals of the second invertor 24 so that the fourth switch 20 and the second invertor 24 are connected in parallel to each other to the second capacitor C22. A data latch circuit 12 is provided having an input terminal connected to the output terminal of the second invertor 24. The conventional chopper comparator has an output terminal 15 connected to an output terminal of the data latch circuit 12. An output voltage Dout appears on the output terminal 15 as a result of the comparison of the input analog signal voltage level to the comparative reference voltage level.
Operations of the above conventional chopper comparator will subsequently be described with reference to FIG. 2. The operations of the above conventional chopper comparator may be considered to be divided into two time periods, for example, first and second time periods. In the first time period, the first, third and fourth switches 1, 19 and 20 are in ON state whilst the second switch 2 is in OFF state. Since the first switch 1 is in ON state, the analog input signal voltage Vin is applied through the first switch 1 to the first capacitor C21. A first short circuit is formed by the third switch 19 between the input and output terminals of the first invertor 23. A second short circuit is also formed by the fourth switch 20 between the input and output terminals of the second invertor 24. The first invertor 23 outputs an output voltage corresponding to the logical threshold voltage VLT23 as an operational point at which input and output voltages of the first invertor 23 are balanced. The second invertor 24 outputs an output voltage corresponding to the logical threshold voltage VLT24 as an operational point at which input and output voltages of the second invertor 24 are balanced. The analog input signal voltage Vin is applied to an input side terminal of the first capacitor C21. The logical threshold voltage VLT23 is generated on an output side terminal of the first capacitor C21. Since the third switch 19 is in ON state, the logical threshold voltage VLT23 is also applied to an input side terminal of the second capacitor C22. The logical threshold voltage VLT24 is generated on an output side terminal of the second capacitor C22. The first capacitor C21 is biased by a voltage corresponding to a difference between the analog input signal voltage Vin and the logical threshold voltage VLT23. The first capacitor C21 is charged in accordance with the difference between the analog input signal voltage Vin and the logical threshold voltage VLT23. The second capacitor C22 is also biased by a voltage corresponding to a difference between the logical threshold voltages VLT23 and VLT24. The second capacitor C22 is charged in accordance with the difference between the logical threshold voltages VLT23 and VLT24. Even if the first and second invertors 23 and 24 are designed to be identical with each other, the logical threshold voltages VLT23 and VLT24 somewhat differ from each other due to unavoidable variations on fabrication processes for the semiconductor integrated circuits. For that reason, the second capacitor C22 is charged in accordance with the difference between the logical threshold voltages VLT23 and VLT24.
In the second time period, the first, third and fourth switches 1, 19 and 20 turn OFF whilst the second switch 2 turns ON. The comparative reference voltage Vref is applied through the second switch 2 to the first capacitor C21. If the analog input signal voltage Vin is higher than the comparative reference voltage Vref, this means that the voltage applied to the input side terminal of the first capacitor C21 is dropped from the analog input signal voltage Vin to the comparative reference voltage Vref. The drop of the voltage level or the potential of the input side terminal of the first capacitor C21 causes a potential drop on the output side terminal of the first capacitor C21 in accordance with the principle of conservation of charge. Namely, the potential of the output side terminal of the first capacitor C21 is, for example, dropped from the logical threshold voltage VLT23 to a voltage VLT23' provided that Vin-VLT23=Vref-VLT23'. The potential of the input terminal of the first invertor 23 is also dropped from the logical threshold voltage VLT23 to the voltage VLT23'. The potential drop on the input terminal of the first invertor 23 causes a rise of the potential of the output terminal of the first invertor 23. The rise of the potential of the output terminal of the first invertor 23 causes a rise of the potential of the input side terminal of the second capacitor C22. The rise of the potential of the input side terminal of the second capacitor C22 causes a rise of the potential of the output side terminal of the second capacitor C22. The rise of the potential of the output side terminal of the second capacitor C22 causes a rise of the potential of the input terminal of the second invertor 24. The rise of the potential of the input terminal of the second invertor 24 causes a drop of the potential of the output terminal of the second invertor 24. The output voltage from the second invertor 24 is then fetched by the data latch circuit 12 before the output voltage from the second invertor 24 is converted into logic levels to be outputted onto the output terminal 15 as the result of the comparison of the analog input signal voltage to the comparative reference voltage.
If, however, the analog input signal voltage Vin is lower than the comparative reference voltage Vref, this means that the voltage applied to the input side terminal of the first capacitor C21 has risen from the analog input signal voltage Vin to the comparative reference voltage Vref. The rise of the voltage level or the potential of the input side terminal of the first capacitor C21 causes a potential rise on the output side terminal of the first capacitor C21 in accordance with the principle of conservation of charge. Namely, the potential of the output side terminal of the first capacitor C21 is, for example, risen from the logical threshold voltage VLT23 to a voltage VLT23' provided that Vin-VLT23=Vref-VLT23'. The potential of the input terminal of the first invertor 23 is also risen from the logical threshold voltage VLT23 to the voltage VLT23'. The potential rise on the input terminal of the first invertor 23 causes a drop of the potential of the output terminal of the first invertor 23. The drop of the potential of the output terminal of the first invertor 23 causes a drop of the potential of the input side terminal of the second capacitor C22. The drop of the potential of the input side terminal of the second capacitor C22 causes a drop of the potential of the output side terminal of the second capacitor C22. The drop of the potential of the output side terminal of the second capacitor C22 causes a drop of the potential of the input terminal of the second invertor 24. The drop of the potential of the input terminal of the second invertor 24 causes a rise of the potential of the output terminal of the second invertor 24. The output voltage from the second invertor 24 is then fetched by the data latch circuit 12 before the output voltage from the second invertor 24 is converted into logic levels to be outputted onto the output terminal 15 as the result of the comparison of the analog input signal voltage to the comparative reference voltage.
FIG. 3 is a diagram illustrative of input output characteristics L1 and output characteristics L2 and L3 of the invertor in the above conventional chopper comparator. The input-output characteristics for the logical threshold voltage of the invertor are represented by a line L1. The output characteristic of the invertor when supplied with a power voltage of VDD is represented by a curve L2. The output characteristic of the invertor when supplied with a power voltage of VDD' is represented by a curve L3. If the power voltage is VDD in the first time period and then unintentionally dropped to a voltage VDD' in the second time period, then the logical threshold voltage VLT (point A) having been in the first time period is also dropped to a voltage VLT' (point B). The output characteristic L2 having been in the first time period is also changed to the output characteristic L3. If the input voltage to be inputted to the invertor remains corresponding to the logical threshold voltage VLT through the first and second time periods, then the output voltage from the invertor corresponds to the point A on the output voltage curve L2 in the first time period and then is dropped to a voltage corresponding to the point C on the output voltage curve L3 in the second time period.
If for example, the input voltage to be inputted into the invertor corresponds to the point A in the first time period before the input voltage is dropped to correspond to the point D due to the variation of the logical threshold voltage by the power voltage drop, then the output voltage from the invertor corresponds to the point D2 on the curve L3. If, however, no power voltage drop appears, then the output voltage corresponds to the point D1 on the curve L2. Namely, if the power voltage drop appears, the result of the comparison of the analog input signal voltage to the comparative reference voltage is opposite to the correct one. If the power voltage drop appears, the malfunction of the chopper comparator may appear.
Further, if a difference between the analog input signal voltage and the comparative reference voltage is made narrower by the power voltage drop, then there is made longer a time period when the output voltage from the invertor remains at an intermediate voltage level between the power voltage level and the ground level. As a result, a time period flowing a punch through current through the invertor is made longer. When the operational point of the invertor remains at the intermediate voltage level, the invertor shows an amplification factor of about 10. If the difference between the analog input signal and the comparative reference voltage is small, then it is required to make a series connection of plural invertors in order to amplify the output voltage up to the logic level. This results in an increased power.
Under the above circumstances, it had been required to develop a novel chopper comparator showing high speed and low power operations fee of any malfunction under variation of logical threshold voltage of invertor in a sampling time period for sampling analog input signal voltage and comparative reference voltage and other time period.